A. Technical Field
The present invention relates to generating digital clocking schemes, and more particularly, to systems, devices, and methods of generating fractional clock signals by non-integer frequency division.
B. Background of the Invention
A wide variety of modern high-speed communications in digital and mixed-signal circuits require the conversion of a single reference clock signal having a fixed frequency into multiple clock signals having different and typically slower frequencies. Clock frequencies that are integer multiples of each other are oftentimes generated by circuits that combine a phase-locked loop (PLL) and a frequency divider having a fixed integer division ratio to scale from one frequency to another. PLLs compare the output of a voltage controllable oscillator (VCO) to the output of a fixed-frequency reference oscillator and adjust the VCO frequency to that of the reference oscillator. PLLs can output a frequency that is a multiple N of the reference oscillator frequency, in this case, dividing VCO output clock by N before comparing it with the reference oscillator output.
Circuits that generate non-integer ratios are limited to a few non-integer ratios, because complexity increases significantly when clock signal frequencies to be generated are non-integer multiples of each other. Die area and power considerations oftentimes do not allow for the use separate PLLs to generate each clock signal. One existing approach to achieve division by a fraction of an integer combines a single PLL with an input frequency divider and/or a divider in the feedback path to generate clock signal frequencies that are fractional multiples of each other. Other approaches are implemented by using logic circuits with a single PLL and fractional frequency dividers in the feedback path, for example, in frequency synthesizers.
What is needed is a fractional clock generator with a small die area, low power consumption, and a low jitter high performance output.